library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity SF_receive_side_w_test_fifos is
  port( 							
		clk, reset: in std_logic;
		
		--inputs to rcv port mimic FIFOs
		--data FIFOs
		rcv0d_wreq:		std_logic;
		rcv0d_input:	std_logic_vector(7 downto 0);
		
		rcv1d_wreq:		std_logic;
		rcv1d_input:	std_logic_vector(7 downto 0);

		rcv2d_wreq:		std_logic;
		rcv2d_input:	std_logic_vector(7 downto 0);

		rcv3d_wreq:		std_logic;
		rcv3d_input:	std_logic_vector(7 downto 0);

		--length FIFOs
		rcv0l_wreq:		std_logic;
		rcv0l_input:	std_logic_vector(11 downto 0);
		
		rcv1l_wreq:		std_logic;
		rcv1l_input:	std_logic_vector(11 downto 0);

		rcv2l_wreq:		std_logic;
		rcv2l_input:	std_logic_vector(11 downto 0);

		rcv3l_wreq:		std_logic;
		rcv3l_input:	std_logic_vector(11 downto 0);


		--outputs from RecHandle to SF_table_interface
		rcv_port_number_to_xmt: out std_logic_vector(1 downto 0);

		
		--address FIFO signals
		afifo_wreq:		out std_logic;
		afifo_empty: 	in std_logic;
		afifo_input:	out std_logic_vector(7 downto 0);
		
		--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		lfifo_wreq:		out std_logic;
		lfifo_full: 	in std_logic;
		lfifo_input: 	out std_logic_vector(11 downto 0);
	
		--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		dfifo_wreq:		out std_logic;
		dfifo_full: 	in std_logic;
		dfifo_input: 	out std_logic_vector(7 downto 0)
  );  
end SF_receive_side_w_test_fifos;

Architecture arch of SF_receive_side_w_test_fifos is 

------------Signals

		--data FIFOs
		signal rcv0d_rdreq:		std_logic;
--		signal rcv0d_empty:		std_logic;
--		signal rcv0d_full:		std_logic;
		signal rcv0d_output: 	std_logic_vector(7 downto 0);

		signal rcv1d_rdreq:		std_logic;
--		signal rcv1d_empty:		std_logic;
--		signal rcv1d_full:		std_logic;
		signal rcv1d_output: 	std_logic_vector(7 downto 0);

		signal rcv2d_rdreq:		std_logic;
--		signal rcv2d_empty:		std_logic;
--		signal rcv2d_full:		std_logic;
		signal rcv2d_output: 	std_logic_vector(7 downto 0);

		signal rcv3d_rdreq:		std_logic;
--		signal rcv3d_empty:		std_logic;
--		signal rcv3d_full:		std_logic;
		signal rcv3d_output: 	std_logic_vector(7 downto 0);

		--length FIFOs
		signal rcv0l_rdreq:		std_logic;
		signal rcv0l_empty:		std_logic;
--		signal rcv0l_full:		std_logic;
		signal rcv0l_output: 	std_logic_vector(11 downto 0);

		signal rcv1l_rdreq:		std_logic;
		signal rcv1l_empty:		std_logic;
--		signal rcv1l_full:		std_logic;
		signal rcv1l_output: 	std_logic_vector(11 downto 0);

		signal rcv2l_rdreq:		std_logic;
		signal rcv2l_empty:		std_logic;
--		signal rcv2l_full:		std_logic;
		signal rcv2l_output: 	std_logic_vector(11 downto 0);

		signal rcv3l_rdreq:		std_logic;
		signal rcv3l_empty:		std_logic;
--		signal rcv3l_full:		std_logic;
		signal rcv3l_output: 	std_logic_vector(11 downto 0);


------------Components
	component SF_receive_side is
	port(
		clk, reset: in std_logic;
		--inputs from rcv to SF_rcv_interface
		rcv0_data, 	rcv1_data, 	rcv2_data, 	rcv3_data: in std_logic_vector(7 downto 0);
		rcv0_length,rcv1_length,rcv2_length,rcv3_length: in std_logic_vector(11 downto 0);
		rcv0_qempty,rcv1_qempty,rcv2_qempty,rcv3_qempty: in std_logic;
	
		--outputs to rcv from SF_rcv_interface
		rcv0_drdreq, 	rcv1_drdreq, 	rcv2_drdreq, 	rcv3_drdreq: out std_logic;
		rcv0_lrdreq, 	rcv1_lrdreq, 	rcv2_lrdreq, 	rcv3_lrdreq: out std_logic;
	
		--inputs from SF_table_interface to RecHandle
		--there are none
	
		--outputs from RecHandle to SF_table_interface
		rcv_port_number_to_xmt: out std_logic_vector(1 downto 0);
		
		--address FIFO signals
		afifo_wreq:		out std_logic;
		afifo_empty: 	in std_logic;
		afifo_input:	out std_logic_vector(7 downto 0);
		
		--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		lfifo_wreq:		out std_logic;
		lfifo_full: 	in std_logic;
		lfifo_input: 	out std_logic_vector(11 downto 0);
	
		--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		dfifo_wreq:		out std_logic;
		dfifo_full: 	in std_logic;
		dfifo_input: 	out std_logic_vector(7 downto 0)
	);
	end component;

	component FIFO_Data_Length IS  --this is the FIFO holding the packet length value (jacob)
	PORT (
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
	end component;
	
	
	component Data_FIFO IS  --this is the data packet FIFO
	PORT(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
	end component;


	--port maps
	begin
	receive_side: SF_receive_side PORT MAP(
		clk			=> clk,
		reset		=> reset,
		--inputs from rcv to SF_rcv_interface
		rcv0_data	=> rcv0d_output,
		rcv1_data	=> rcv1d_output,
		rcv2_data	=> rcv2d_output,
		rcv3_data	=> rcv3d_output,
		rcv0_length	=> rcv0l_output,
		rcv1_length	=> rcv1l_output,
		rcv2_length	=> rcv2l_output,
		rcv3_length	=> rcv3l_output,
		rcv0_qempty	=> rcv0l_empty,
		rcv1_qempty	=> rcv1l_empty,
		rcv2_qempty	=> rcv2l_empty,
		rcv3_qempty	=> rcv3l_empty,
	
		--outputs to rcv from SF_rcv_interface
		rcv0_drdreq	=> rcv0d_rdreq,
		rcv1_drdreq	=> rcv1d_rdreq,
		rcv2_drdreq	=> rcv2d_rdreq,
		rcv3_drdreq	=> rcv3d_rdreq,
		
		rcv0_lrdreq	=> rcv0l_rdreq,
		rcv1_lrdreq	=> rcv1l_rdreq,
		rcv2_lrdreq	=> rcv2l_rdreq,
		rcv3_lrdreq => rcv3l_rdreq,
	
		--outputs from RecHandle to SF_table_interface
		rcv_port_number_to_xmt	=> rcv_port_number_to_xmt,
		
		--address FIFO signals
		afifo_wreq	=> afifo_wreq,
		afifo_empty	=> afifo_empty,
		afifo_input	=> afifo_input,
		
		--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		lfifo_wreq	=> lfifo_wreq,
		lfifo_full	=> lfifo_full, --: 	in std_logic;
		lfifo_input	=> lfifo_input, --: 	out std_logic_vector(11 downto 0);
	
		--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
		dfifo_wreq	=> dfifo_wreq, --:		out std_logic;
		dfifo_full	=> dfifo_full, --: 	in std_logic;
		dfifo_input	=> dfifo_input	 --: 	out std_logic_vector(7 downto 0)
		
	);

	L_FIFO_0 : FIFO_Data_Length
	Port Map
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv0l_input,
		rdreq 	=> rcv0l_rdreq,
		wrreq	=> rcv0l_wreq,
		empty 	=> rcv0l_empty,
--		full 	=> rcv0l_full,
		q 		=> rcv0l_output,
		usedw 	=> open
	);	
	
	D_FIFO_0 : Data_FIFO
	PORT MAP
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv0d_input,
		rdreq 	=> rcv0d_rdreq,
		wrreq	=> rcv0d_wreq,
--		empty 	=> rcv0d_empty,
--		full 	=> rcv0d_full,
		q 		=> rcv0d_output,
		usedw 	=> open
	);


	L_FIFO_1 : FIFO_Data_Length
	Port Map
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv1l_input,
		rdreq 	=> rcv1l_rdreq,
		wrreq	=> rcv1l_wreq,
		empty 	=> rcv1l_empty,
--		full 	=> rcv1l_full,
		q 		=> rcv1l_output,
		usedw 	=> open
	);	
	
	D_FIFO_1 : Data_FIFO
	PORT MAP
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv1d_input,
		rdreq 	=> rcv1d_rdreq,
		wrreq	=> rcv1d_wreq,
--		empty 	=> rcv1d_empty,
--		full 	=> rcv1d_full,
		q 		=> rcv1d_output,
		usedw 	=> open
	);


	L_FIFO_2 : FIFO_Data_Length
	Port Map
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv2l_input,
		rdreq 	=> rcv2l_rdreq,
		wrreq	=> rcv2l_wreq,
		empty 	=> rcv2l_empty,
--		full 	=> rcv2l_full,
		q 		=> rcv2l_output,
		usedw 	=> open
	);	
	
	D_FIFO_2 : Data_FIFO
	PORT MAP
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv2d_input,
		rdreq 	=> rcv2d_rdreq,
		wrreq	=> rcv2d_wreq,
--		empty 	=> rcv2d_empty,
--		full 	=> rcv2d_full,
		q 		=> rcv2d_output,
		usedw 	=> open
	);


	L_FIFO_3 : FIFO_Data_Length
	Port Map
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv3l_input,
		rdreq 	=> rcv3l_rdreq,
		wrreq	=> rcv3l_wreq,
		empty 	=> rcv3l_empty,
--		full 	=> rcv3l_full,
		q 		=> rcv3l_output,
		usedw 	=> open
	);	
	
	D_FIFO_3 : Data_FIFO
	PORT MAP
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> rcv3d_input,
		rdreq 	=> rcv3d_rdreq,
		wrreq	=> rcv3d_wreq,
--		empty 	=> rcv3d_empty,
--		full 	=> rcv3d_full,
		q 		=> rcv3d_output,
		usedw 	=> open
	);


end arch;